1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method therefor, for example, a NAND flash memory including a selection gate transistor.
2. Description of the Related Art
A NAND flash memory has a NAND string in which a drain-side selection gate transistor and a source-side selection gate transistor are arranged at both ends of memory transistors connected in series with each other. The drain-side selection gate transistor is connected to a bit line through a bit line contact electrode. The source-side selection gate transistor is connected to a source line through a source line contact electrode. The NAND strings are arranged in a direction orthogonal to a direction in which memory cells are connected in series with each other. Adjacent NAND strings are arranged such that drain-side selection transistors of the NAND strings are adjacent to each other or source-side selection transistors of the NAND strings are adjacent to each other.
A method of manufacturing a conventional NAND flash memory is described in Jpn. Pat. Appln. KOKAI Publication No. 2002-231832.
In this manufacturing method, if a space between a memory cell transistor and a selection gate transistor adjacent thereto (space between MG and SG1) and a space between adjacent selection gate transistors (space between SG1 and SG2) are larger than a space between the adjacent memory transistors (space between MG and MG) each, halo ion implantation is consequently performed at a high concentration between MG and SG1 and between SG1 and SG2. As a result, a threshold voltage of the memory cell transistor arranged adjacent to the selection gate transistor disadvantageously excessively rises.
Aside from this, on a semiconductor substrate on which the memory cell transistors and the selection gate transistors are formed, a peripheral circuit including a peripheral transistor is formed.
A semiconductor memory device in which a film thickness of a sidewall insulating film of the peripheral transistor is larger than a film thickness of a sidewall insulating film of the memory cell transistor is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2005-197308.
However, when the sidewall insulating film formed between the adjacent selection gate transistors (between SG1 and SG2) increases, a contact electrode connected to a bit line is disadvantageously brought into contact with the sidewall insulating film. In order to avoid this, the space between SG1 and SG2 must be increased. In this case, the length of the NAND cell increases, and, consequently, a chip area disadvantageously increases.